1. Field of the Invention
The invention relates generally to a digital-to-analog converter, and more particularly, to a current-steering digital-to-analog converter capable of minimizing glitch noises at an output terminal.
2. Description of the Prior Art
As a very large scale integration (VLSI) technology is rapidly growing according to Moore""s law, it is possible to integrate analog and digital systems, which was realized on a conventional board, on a single chip. Therefore, the digital-to-analog converter (DAC), the interface block between the analog and digital systems, is considered as the key component completing the integrated system design.
DACs can be classified into a DAC for voice signal and a DAC for image signal based on the signal bandwidth. The DAC for voice signal processing has a sigma-delta structure for more than 16b resolution at low conversion rate. On the other hands, the DAC for image signal processing within the digital TV, HDTV, and medical equipment has a current-steering structure that can be implemented at high speed. A medium low-speed DAC having a R-2R ladder structure is applied to a portable measurement apparatus, an industry mechanical control apparatus, a digital control amplifier, and the like.
Usually, most high-speed and high-resolution DAC adopt a current-steering structure for its good linearity, operating speed and cost efficiency. There has recently been developed a current-steering DAC having a high static performance of over 12 bits resolution.
However, there is a problem that the dynamic performance of the current-steering DAC is abruptly degraded by glitch noise occurring at the output terminal, when the output signal frequency is increased to several dozens of MHz band.
Since the glitch noise is mainly caused by switch control signals, a current cell driving circuit generating the switch control signals is the critical block determining the dynamic performance of the current-steering DAC.
Therefore, examples for reducing the glitch noise include U.S. Pat. No. 5,463,394 issued on Oct. 31, 1995 (xe2x80x98Current Switch for a High Speed DACxe2x80x99), U.S. Pat. No. 6,295,012 issued on Aug. 25, 1999 (xe2x80x98CMOS DAC with High Impedance Differential Current Driversxe2x80x99), xe2x80x98A 12bit 200 MHz Low Glitch CMOS D/A Converterxe2x80x99 written in xe2x80x98CICC98xe2x80x99 by xe2x80x98A Van Bosch, et al.xe2x80x99 (June 1998) and xe2x80x98A 10-bit 1-Gsample/s Nyquist Current-Steering CMOS D/A Converterxe2x80x99 written in xe2x80x98IEEE, JSSCxe2x80x99 by xe2x80x98A Van Bosch, et al.xe2x80x99 (March 2001).
In order to reduce the glitch noise, the above prior arts employed methods of adjusting a cross point of differential control signals or reducing a transition time of the signals. As these methods, however, transit the control signals over the full range (from 0V to VDD or from VDD to OV) corresponding to the amount of the supply power voltage, there is a limit in reducing the glitch noise due to an influence of the control signals to the final output signal. Further, there was published a technology of reducing the amplitude of the control signals through voltage limiters. However, the conventional voltage limiters increase the transition time and make it difficult to be employed in high-speed applications.
The present invention is contrived to solve the above problems, and an object of the present invention is to provide a current cell driving circuit in a digital-to-analog converter (DAC) that can effectively limit the amplitude of the control signals and minimize the transition time, while not compromising the power consumption or the circuit area.
In order to accomplish the above object, a current cell driving circuit according to the present invention comprises a latch means for latching input signals depending on a clock signal to output first and second latch signals; and a voltage limiter means for limiting the first and second latch signals to a given level to output the first and second differential control signals.